Integrated circuits may be formed using various photolithographic techniques. Such techniques typically involve exposing a photoresist layer to a light source through a patterned photo-mask. In general, the final pattern formed onto the photoresist layer does not precisely match the designed pattern for which the final pattern was formed. This is caused by various photolithographic process parameters such as the resolution of the light source. It is important to ensure that the final printed pattern is not so far from the designed pattern that functionality of the circuit is adversely affected.
Various procedures are used to ensure that the final printed pattern is within the desired tolerance range of the target pattern. One process that is used is referred to as Optical Proximity Correction (OPC). The OPC process typically involves applying a set of rules to determine target points along edges of the design pattern. The design pattern is then modified so that a contour resulting from a simulation of the printout of the modified design pattern approximates the OPC target points.
Use of target points that were determined based on application a set of rules is a time consuming process. The designer may have to make several modifications to the target points based on experience, simulation, and testing in order to bring the final printout within the design specification. Accordingly, it is desirable to have a method of determining the placement of OPC target points that reduces the amount of time a designer or engineer must spend on fine tuning the design pattern to achieve the desired target pattern.